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Dissertation Defense – Shreya Dwarakanath
MSE Grad Presentation
Thursday, April 2, 2020 - 10:45am
"Ultra-Low Dielectric Constant and Ultra-Thin Polymer Dielectric Materials, Processes and Reliability for Ultra-High Bandwidth Computing Applications"
via BlueJeans Video Conferencing https://bluejeans.com/907986217
Prof. Rao Tummala, Advisor, ECE/MSE
Prof. Mark Losego, Co-Advisor, MSE
Prof. C.P. Wong, MSE
Prof. Natalie Stingelin, MSE/ChBE
Prof. Raj Pulugurtha, Florida International University
"Ultra-Low Dielectric Constant and Ultra-Thin Polymer Dielectric Materials, Processes and Reliability for Ultra-High Bandwidth Computing Applications"Abstract:
The increase in the number of connected devices in homes, cars and offices coupled with the growth of advanced data processing algorithms enabled by artificial intelligence (AI) has been driving an unprecedented need for ultra-high bandwidth computing. At the package level, the bandwidth increase can be achieved by increasing the number of input-output (I/O) connections or by increasing the data rate for each connection. The number of I/Os depends on the wiring density supported by each layer and the number of layers. These layers have to be vertically spaced at ultra-small distances to enable high-wiring density. The data rate is primarily influenced by the dielectric constant or Dk. Hence, the focus of this research is to develop ultra-low Dk and ultra-thin polymer dielectric materials, processes and reliability to meet the next-generation computing needs of ultra-high bandwidth. Silicon back-end-of line (BEOL) wiring has significant limitations such as high RC delays because of the choice of dielectric materials and cost. Current organic materials and processes are limited by their incapacity to scale to fine-features because of thick dielectric materials and poor dimensional stability of the core. This research is focused on overcoming the limitations of current approaches and demonstrating the potential for ultra-low Dk, ultra-thin polymer dielectrics to signal at higher data rates, establishing process guidelines for panel-scalable and low-cost processes and investigating the reliability of ultra-thin, ultra-low Dk dielectrics/copper interfaces, thus leading to enhanced electrical performance and lower cost compared to silicon BEOL and current organic RDL.
The specific objectives of this thesis are to a) develop ultra-low-Dk (< 3.0) and ultra-thin (2-5 µm) polymer dielectric materials with optimal properties for high-signal speed, b) develop panel-scale processes for ultra-thin dielectrics with high surface planarity capable of supporting fine line/spaces of < 2 µm line width/space and < 5 µm diameter vias and, c) investigate the thermo-mechanical and chemical reliability of polymer/copper interfaces. In summary, this thesis explores polymer material classes in their compatibility for high-density RDL wiring in terms of their material properties, ease of fabricating fine-pitch features on planar and smooth surfaces and finally, in creating reliable copper/polymer interfaces with good adhesion.